This is a role for engineers who enjoy pushing FPGAs to their limits—where MHz matter, timing margins are tight, and LUTs must be used with precision.
19th June, 2025
Join one of the most technically advanced FPGA teams in Australia, designing cutting-edge systems where you'll be working on high-performance, timing-critical designs.
This is a role for engineers who enjoy pushing FPGAs to their limits—where MHz matter, timing margins are tight, and LUTs must be used with precision.
This is a senior position and requires you to have 10+ years FPGA design experience.
What You’ll Work On:
Architect and implement FPGA designs running at higher clock frequencies, with strict timing and deterministic performance requirements.
Optimise datapaths for throughput and latency, balancing pipeline depth and logic resource usage (LUTs, FFs, DSPs).
Drive the complete design cycle—from RTL through synthesis, timing closure, and lab validation on real hardware.
Debug complex interactions between FPGAs, high-speed memory interfaces (DDR3/DDR4)
Collaborate with a multidisciplinary team of hardware, software, and systems engineers on highly integrated products.
Your Skillset:
10+ years FPGA design experience
Good understanding of VHDL / Verilog for high-speed designs
Understanding of synchronous design techniques and how to keep designs stable when things get complex
Familiarity with Vivado timing analysis, debugging, and scripting (Tcl/Python) for build/test automation.
Hands-on with hardware validation and system-level debugging using scopes, analysers, and JTAG tools.
The Other Stuff:
The position is based in Sydney CBD
Permanent residency or citizenship preferred, but sponsorship is available for standout candidates
Onsite or video interviews available
Please feel free to get in touch with any questions.
Luke Johnson Recruitment Consultant P: 0466 210 441 E: luke@codematix.com.au
You can find out more about Codematix Pty. Ltd. by visiting codematix.com.au
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